Renesas H8 Series Hardware Manual page 593

Upper Address: H'FF
Lower Register
Address Name Bit 7
H'80
H'81
H'82
H'83
H'84
H'85
H'86 LVDCR LVDE
H'87 LVDSR OVF
H'88
H'89
H'8A
H'8B
H'8C ECPWCRH ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Asynchronous
H'8D ECPWCRL ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 event counter
H'8E ECPWDRH ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0
H'8F ECPWDRL ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
H'90 WEGR WKEGS7
H'91 SPCR —
H'92 AEGSR AHEGS1
H'93
H'94 ECCR ACKH1
H'95 ECCSR OVH
H'96 ECH ECH7
H'97 ECL ECL7
H'98
H'99
H'9A
H'9B
H'9C
H'9D
H'9E
H'9F
Bit 6 Bit 5 Bit 4
— VINTDSEL VINTUSEL
— — —
WKEGS6 WKEGS5 WKEGS4
— SPC32 —
AHEGS0 ALEGS1 ALEGS0
ACKH0 ACKL1 ACKL0
OVL — CH2
ECH6 ECH5 ECH4
ECL6 ECL5 ECL4
Appendix B Internal I/O Registers
Bit Names
Bit 3 Bit 2
LVDSL LVDRE
VREFSEL —
WKEGS3 WKEGS2
SCINV3 SCINV2
AIEGS1 AIEGS0
PWCK2 PWCK1
CUEH CUEL
ECH3 ECH2
ECL3 ECL2
Rev. 7.00 Mar 10, 2005 page 551 of 652
Bit 1 Bit 0 Module Name
LVDDE LVDUE Low-voltage
detect circuit *
LVDDF LVDUF
WKEGS1 WKEGS0 System control
— — SCI3
ECPWME — Asynchronous
event counter
PWCK0 —
CRCH CRCL
ECH1 ECH0
ECL1 ECL0
REJ09B0042-0700