Renesas H8 Series Hardware Manual page 562

Section 16 Electrical Characteristics
Item Symbol
Input pin high t
IH
width
Input pin low t
IL
width
UD pin minimum t
UDH
transition width
t
UDL
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. These characteristics are given as ranges between minimum and maximum values in
order to account for factors such as temperature, power supply voltage, and variation
among production lots. When designing systems, make sure to give due consideration
to the SPEC range. Please contact a Renesas sales or support representative for
actual performance data on the product.
Table 16.23 Serial Interface (SCI3) Timing
V = 2.7 V to 5.5 V, AV
CC
Item
Input clock Asynchronous
cycle
Clocked synchronous
Input clock pulse width
Transmit data delay time
(clocked synchronous)
Receive data setup time
(clocked synchronous)
Receive data hold time
(clocked synchronous)
Rev. 7.00 Mar 10, 2005 page 520 of 652
REJ09B0042-0700
Applicable
Pins Min
, , 2
I R Q 0 I R Q 1
, ,
I R Q 3 I R Q 4
IRQAEC,
to
W K P 0
, TMIC,
W K P 7
TMIF, TMIG,
A D T R G
AEVL, AEVH 0.5
, , 2
I R Q 0 I R Q 1
, ,
I R Q 3 I R Q 4
IRQAEC,
to
W K P 0
, TMIC,
W K P 7
TMIF, TMIG,
A D T R G
AEVL, AEVH 0.5
UD 4
= 2.7 V to 5.5 V, V
CC
Symbol Min
t 4
scyc
6
t 0.4
SCKW
t —
TXD
t 150.0
RXS
t 150.0
RXH
Values
Typ Max Unit
— — t
cyc
t
subcyc
— — t
OSC
— — t
cyc
t
subcyc
— — t
OSC
— — t
cyc
t
subcyc
= AV = 0.0 V, unless otherwise specified
SS SS
Values
Typ Max Unit
— — t or
cyc
t
subcyc
— —
— 0.6 t
scyc
— 1 t or
cyc
t
subcyc
— — ns
— — ns
Reference
Test Condition Figure
Figure 16.3
Figure 16.3
Figure 16.6
Test Reference
Condition Figure
Figure 16.4
Figure 16.4
Figure 16.5
Figure 16.5
Figure 16.5