Renesas H8 Series Hardware Manual page 62

Section 1 Overview
FP-80A
Type Symbol TFP-80C FP-80B TLP-85V
OSC 10
Clock
1
pins
OSC 9
2
X 6
1
X 7
2
12
System
R E S
control
TEST 11
Interrupt 72
I R Q
0
pins 76
I R Q
1
5
I R Q
3
3
I R Q
4
IRQAEC 60
Rev. 7.00 Mar 10, 2005 page 20 of 652
REJ09B0042-0700
Pin No.
Pad
No. *
12 F2 11
11 E3 10
8 D3 6
9 D2 7
14 F3 13
13 E2 12
74 C5 73
78 B3 77
7 D1 5
5 B2 3
62 C10 61
Pad Pad
1 No. * 2 No. * 3
I/O
12 10 Input
11 9 Output
7 6 Input
8 7 Output
14 12 Input
13 11 Input
74 72 Input
78 76
6 5
4 3
62 60 Input
Name and Functions
These pins connect to a
crystal or ceramic
oscillator, or can be used
to input an external clock.
See section 4, Clock
Pulse Generators, for a
typical connection
diagram.
These pins connect to a
32.768-kHz or 38.4-kHz *
crystal oscillator.
See section 4, Clock
Pulse Generators, for a
typical connection
diagram.
Reset: When this pin is
driven low, the chip is
reset
Test pin: This pin is
reserved and cannot be
used. It should be
connected to V .
SS
IRQ interrupt request 0,
1, 3, and 4: These are
input pins for edge-
sensitive external
interrupts, with a selection
of rising or falling edge
Asynchronous event
counter event signal:
This is an interrupt input
pin for enabling
asynchronous event
input.
On the H8/38124 Group,
this must be fixed at V
CC
or GND because the
oscillator is selected by
the input level during
resets. Refer to section 4,
Clock Pulse Generators,
for information on the
selection method.
5