Renesas H8 Series Hardware Manual page 608

Appendix B Internal I/O Registers
ECCSR—Event Counter Control/Status Register
Bit 7
OVH
Initial value 0
Read/Write R/W
Counter Overflow H
0 ECH has not overflowed
1 ECH has overflowed
Rev. 7.00 Mar 10, 2005 page 566 of 652
REJ09B0042-0700
6 5

OVL CH2
0 0
R/W R/W R/W
Channel Select
0
1
Counter Overflow L
0 ECL has not overflowed
1 ECL has overflowed
H'95
4 3 2
CUEH CUEL
0 0 0
R/W R/W
Counter Reset Control L
0
1
Counter Reset Control H
0 ECH is reset
1 ECH reset is cleared and
count-up function is enabled
Count-up Enable L
0 ECL event clock input is disabled.
ECL value is held
1 ECL event clock input is enabled
Count-up Enable H
0 ECH event clock input is disabled.
ECH value is held
1 ECH event clock input is enabled
ECH and ECL are used together as a single-
channel 16-bit event counter
ECH and ECL are used as two independent
8-bit event counter channels
AEC
1 0
CRCH CRCL
0 0
R/W R/W
ECL is reset
ECL reset is cleared
and count-up function
is enabled