Timer Operation - Renesas H8 Series Hardware Manual

Section 9 Timers
Clock Stop Register 1 (CKSTPR1)
7
Bit:

Initial value: 1

Read/Write:
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer C is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 1—Timer C Module Standby Mode Control (TCCKSTP)
Bit 1 controls setting and clearing of module standby mode for timer C.
TCCKSTP Description
0 Timer C is set to module standby mode
1 Timer C module standby mode is cleared
9.3.3

Timer Operation

Interval Timer Operation
When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit
interval timer.
Upon reset, TCC is initialized to H'00 and TMC to H'18, so TCC continues up-counting as an
interval up-counter without halting immediately after a reset. The timer C operating clock is
selected from seven internal clock signals output by prescalers S and W, or an external clock input
at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC.
TCC up/down-count control can be performed either by software or hardware. The selection is
made by bits TMC6 and TMC5 in TMC.
After the count value in TCC reaches H'FF (H'00), the next clock input causes timer C to overflow
(underflow), setting bit IRRTC in IRR2 to 1. If IENTC = 1 in interrupt enable register 2 (IENR2),
a CPU interrupt is requested.
At overflow (underflow), TCC returns to H'00 (H'FF) and starts counting up (down) again.
Rev. 7.00 Mar 10, 2005 page 258 of 652
REJ09B0042-0700
6 5

S32CKSTP ADCKSTP TGCKSTP
1 1

R/W R/W
4 3 2
TFCKSTP TCCKSTP TACKSTP
1 1 1
R/W R/W
1 0
1 1
R/W R/W
(initial value)