Renesas H8 Series Hardware Manual page 606

Appendix B Internal I/O Registers
AEGSR—Input Pin Edge Select Register
Bit 7
AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1
Initial value 0
Read/Write R/W
AEC Edge Select L
Bit 5
ALEGS1
0
0
1
1
AEC Edge Select H
Bit 7 Bit 6
AHEGS1 AHEGS0
0
0
1
1
Rev. 7.00 Mar 10, 2005 page 564 of 652
REJ09B0042-0700
6 5
0 0
R/W R/W
Event Counter PWM Enable/Disable,
IRQAEC Select/Deselect
0 AEC PWM halted, IRQAEC selected
1
AEC PWM operation enabled, IRQAEC deselected
IRQAEC Edge Select
Bit 3 Bit 2
AIEGS1 AIEGS0
0 0
0 1
1 0
1 1
Bit 4
ALEGS0
0 Falling edge on AEVL pin is sensed
1 Rising edge on AEVL pin is sensed
0 Both edges on AEVL pin are sensed
1 Use prohibited
0 Falling edge on AEVH pin is sensed
1 Rising edge on AEVH pin is sensed
0 Both edges on AEVH pin are sensed
1 Use prohibited
H'92
4 3
0 0
R/W R/W
Description
Falling edge on IRQAEC pin is sensed
Rising edge on IRQAEC pin is sensed
Both edges on IRQAEC pin are sensed
Use prohibited
Description
Description
2 1
AIEGS0 ECPWME
0 0
R/W R/W R/W
AEC
0

0