Renesas H8 Series Hardware Manual page 166

Section 5 Power-Down Modes
Bit 3—Low Speed on Flag (LSON)
This bit chooses the system clock (φ) or subclock (φ
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON Description
0 The CPU operates on the system clock (φ)
1 The CPU operates on the subclock (φ
Bit 2—Reserved
Bit 2 is reserved: it is always read as 1 and cannot be modified.
Bits 1 and 0—Active (Medium-Speed) Mode Clock Select (MA1, MA0)
Bits 1 and 0 choose φ
speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-
speed) mode or subactive mode.
Bit 1 Bit 0
MA1 MA0
0 0
0 1
1 0
1 1
System Control Register 2 (SYSCR2)
Bit 7

Initial value 1

Read/Write
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5—Reserved
These bits are reserved; they are always read as 1, and cannot be modified.
Rev. 7.00 Mar 10, 2005 page 124 of 652
REJ09B0042-0700
/128, φ /64, φ /32, or φ
osc osc osc
Description
φ
/16
osc
φ
/32
osc
φ
/64
osc
φ
/128
osc
6 5
 
1 1
 
) as the CPU operating clock when watch
SUB
)
SUB
/16 as the operating clock in active (medium-
osc
4 3
NESEL DTON MSON
1 0
R/W R/W R/W
(initial value)
(initial value)
2 1 0
SA1 SA0
0 0 0
R/W R/W