Renesas H8 Series Hardware Manual page 126

Section 3 Exception Handling
Bit 1—Timer C Interrupt Enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC Description
0 Disables timer C interrupt requests
1 Enables timer C interrupt requests
Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC Description
0 Disables asynchronous event counter interrupt requests
1 Enables asynchronous event counter interrupt requests
For details of SCI3 interrupt control, see section 10.2.6 Serial control register 3 (SCR3).
Interrupt Request Register 1 (IRR1)
Bit 7
IRRTA
Initial value 0
R/(W) *
Read/Write
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
IRQAEC, IRQ , IRQ
4 3
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
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REJ09B0042-0700
6 5
 

1

W
, IRQ , or IRQ interrupt is requested. The flags are not cleared
1 0
4 3
IRRI4 IRRI3 IRREC2
0 0
R/(W) * R/(W) * R/(W) *
(initial value)
(initial value)
2 1 0
IRRI1 IRRI0
0 0 0
R/(W) * R/(W) *