Timer C Operation States - Renesas H8 Series Hardware Manual

8-bit single-chip microcomputer

Hide thumbs Also See for H8 Series:

Table of Contents

Section 9 Timers

Timer C Operation States

Table 9.6 summarizes the timer C operation states.

Timer C Operation States

Operation Mode

Note: * When φw/4 is selected as the TCC internal clock in active mode or sleep mode, since the

system clock and internal clock are mutually asynchronous, synchronization is maintained

by a synchronization circuit. This results in a maximum count cycle error of 1/φ (s). When

the counter is operated in subactive mode or subsleep mode, either select φw/4 as the

internal clock or select an external clock. The counter will not operate on any other

internal clock. If φw/4 is selected as the internal clock for the counter when φw/8 has been

selected as subclock φ

the operation of the least significant bit is unrelated to the operation of the counter.

Rev. 7.00 Mar 10, 2005 page 260 of 652

REJ09B0042-0700

Functions Functions Halted

Functions Retained

, the lower 2 bits of the counter operate on the same cycle, and

Functions Retained