Renesas H8 Series Hardware Manual page 600

Appendix B Internal I/O Registers
EBR—Erase Block Register
Bit 7

Initial value 0

Read/Write
Note: Set the bit of EBR to H'00 when erasing.
FENR—Flash Memory Enable Register
Bit 7
FLSHE
Initial value 0
Read/Write R/W
Flash Memory Control Register Enable
0 The flash memory control register cannot be accessed
1 The flash memory control register can be accessed
Rev. 7.00 Mar 10, 2005 page 558 of 652
REJ09B0042-0700
6 5 4
 
EB4
0 0 0
 
R/W
Blocks 4 to 0
0 When a block of EB4 to EB0 is not selected (initial value)
1 When a block of EB4 to EB0 is selected
6 5 4
  
0 0 0
  
H'F023
3 2
EB3 EB2 EB1
0 0
R/W R/W R/W
H'F02B
3 2
 
0 0
 
Flash Memory
1 0
EB0
0 0
R/W
Flash Memory
1 0
 
0 0
 