Renesas H8 Series Hardware Manual page 581

Mnemonic
ROTL.B Rd
ROTR.B Rd
BSET #xx:3, Rd
BSET #xx:3, @Rd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @Rd
BSET Rn, @aa:8
BCLR #xx:3, Rd
BCLR #xx:3, @Rd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @Rd
BCLR Rn, @aa:8
BNOT #xx:3, Rd
BNOT #xx:3, @Rd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @Rd
BNOT Rn, @aa:8
Operation
B
C
b b
7 0
B
b b
7 0
B (#xx:3 of Rd8) ← 1
B (#xx:3 of @Rd16) ← 1
B (#xx:3 of @aa:8) ← 1
B (Rn8 of Rd8) ← 1
B (Rn8 of @Rd16) ← 1
B (Rn8 of @aa:8) ← 1
B (#xx:3 of Rd8) ← 0
B (#xx:3 of @Rd16) ← 0
B (#xx:3 of @aa:8) ← 0
B (Rn8 of Rd8) ← 0
B (Rn8 of @Rd16) ← 0
B (Rn8 of @aa:8) ← 0
B (#xx:3 of Rd8) ←
(#xx:3 of Rd8)
B (#xx:3 of @Rd16) ←
(#xx:3 of @Rd16)
B (#xx:3 of @aa:8) ←
(#xx:3 of @aa:8)
B (Rn8 of Rd8) ←
(Rn8 of Rd8)
B (Rn8 of @Rd16) ←
(Rn8 of @Rd16)
B (Rn8 of @aa:8) ←
(Rn8 of @aa:8)
Appendix A CPU Instruction Set
Addressing Mode/
Instruction Length (bytes)
2
2
C
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
Rev. 7.00 Mar 10, 2005 page 539 of 652
Condition Code
I H N Z V C
 
0 2
 
0 2
      2
      8
      8
      2
      8
      8
      2
      8
      8
      2
      8
      8
      2
      8
      8
      2
      8
      8
REJ09B0042-0700