Renesas H8 Series Hardware Manual page 419

Sender
Receiver A
(ID = 01)
Serial
data
Figure 10.16 Example of Inter-Processor Communication Using Multiprocessor Format
There is a choice of four data transfer formats. If a multiprocessor format is specified, the parity
bit specification is invalid. See table 10.11 for details.
For details on the clock used in multiprocessor communication, see section 10.3.2, Operation in
Asynchronous Mode.
• Multiprocessor transmitting
Figure 10.17 shows an example of a flowchart for multiprocessor data transmission. This
procedure should be followed for multiprocessor data transmission after initializing SCI3.
Communication line
Receiver B
(ID = 02)
H'01
(MPB = 1)
ID transmission cycle
(specifying the receiver)
(Sending Data H'AA to Receiver A)
Section 10 Serial Communication Interface
Receiver C
(ID = 03)
H'AA
(MPB = 0)
Data transmission cycle
(sending data to the receiver
specified by the ID)
Rev. 7.00 Mar 10, 2005 page 377 of 652
Receiver D
(ID = 04)
MPB: Multiprocessor bit
REJ09B0042-0700