Renesas H8 Series Hardware Manual page 392

Section 10 Serial Communication Interface
Table 10.4 Relation between n and Clock
n Clock
φ
0
φw/2 *
1
/φw *
0
φ/16
2
φ/64
3
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ φ φ φ (MHz)
OSC (MHz)
0.0384 *
0.0192
2 1
2.4576 1.2288
4 2
10 5
16 8
20 10
Note: * When SMR is set up to CKS1 = 0, CKS0 = 1.
Rev. 7.00 Mar 10, 2005 page 350 of 652
REJ09B0042-0700
CKS1
0
2
0
1
1
Maximum Bit Rate
(bit/s)
600
31250
38400
62500
156250
250000
312500
SMR Setting
CKS0
0
1
0
1
Setting
n N
0 0
0 0
0 0
0 0
0 0
0 0
0 0