Renesas H8 Series Hardware Manual page 584

Appendix A CPU Instruction Set
Mnemonic
JSR @Rn
JSR @aa:16
JSR @@aa:8
RTS
RTE
SLEEP
LDC #xx:8, CCR
LDC Rs, CCR
STC CCR, Rd
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
EEPMOV
Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0.
(3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation.
(4) The number of states required for execution is 4n + 9 (n = value of R4L). 4n + 8 for HD64F38024,
H8/38024S Group, and H8/38124 Group.
(5) Set to 1 if the divisor is negative; otherwise cleared to 0.
(6) Set to 1 if the divisor is zero; otherwise cleared to 0.
Rev. 7.00 Mar 10, 2005 page 542 of 652
REJ09B0042-0700
Operation
 SP−2 → SP
PC → @SP
PC ← Rn16
 SP−2 → SP
PC → @SP
PC ← aa:16
 SP−2 → SP
PC → @SP
PC ← @aa:8
 PC ← @SP
SP+2 → SP
 CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
 Transit to sleep mode.
B #xx:8 → CCR
B Rs8 → CCR
B CCR → Rd8
B CCR∧#xx:8 → CCR
B CCR∨#xx:8 → CCR
B CCR⊕#xx:8 → CCR
 PC ← PC+2
 if R4L≠0
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L−1 → R4L
Until R4L=0
else next;
Addressing Mode/
Instruction Length (bytes)
2
4
2
2
2
2
2
2
2
Condition Code
I H N Z V C
      6
      8
      8
2       8
2 10
2       2
2
2
      2
2
2
2
2       2
4       (4)