Renesas H8 Series Hardware Manual page 445

Bit 7—Clock Select (CKS)
Bit 7 sets the A/D conversion speed.
Bit 7
CKS Conversion Period
0 62/φ (initial value)
1 31/φ
Notes: 1. With the H8/38024, H8/38024S, and H8/38024F-ZTAT operation cannot be guaranteed
if the conversion time is less than 12.4 µs. Make sure to select a setting that gives a
conversion time of 12.4 µs or more.
With the H8/38124 Group operation cannot be guaranteed if the conversion time is less
than 6.2 µs. Make sure to select a setting that gives a conversion time of 6.2 µs or
more.
2. H8/38124 Group only.
Bit 6—External Trigger Select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE Description
0 Disables start of A/D conversion by external trigger
1 Enables start of A/D conversion by rising or falling edge of external trigger at pin
A D T R G
Note: * The external trigger (
select register (IEGR) in section 3.3.2 for details.
Bits 5 and 4—Reserved
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
*
) edge is selected by bit IEG4 of IEGR. See 1. IRQ edge
A D T R G
Conversion Time
φ φ φ φ = 1 MHz φ φ φ φ = 5 MHz
62 µs 12.4 µs
1
— *
31 µs
Rev. 7.00 Mar 10, 2005 page 403 of 652
Section 12 A/D Converter
φ φ φ φ = 10 MHz *
6.2 µs
1
— *
(initial value)
REJ09B0042-0700
2