Renesas H8 Series Hardware Manual page 326

Section 9 Timers
Input Capture Register GF (ICRGF)
7
Bit:
ICRGF7
Initial value: 0
R
Read/Write:
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ
ICRGF is initialized to H'00 upon reset.
Input Capture Register GR (ICRGR)
7
Bit:
ICRGR7
Initial value: 0
Read/Write: R
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 0 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ
ICRGR is initialized to H'00 upon reset.
Rev. 7.00 Mar 10, 2005 page 284 of 652
REJ09B0042-0700
6 5
ICRGF6 ICRGF5
0 0
R R
(when the noise canceler is not used).
SUB
6 5
ICRGR6 ICRGR5
0 0
R R
(when the noise canceler is not used).
SUB
4 3
ICRGF4 ICRGF3 ICRGF2
0 0
R
R
4 3
ICRGR4 ICRGR3 ICRGR2
0 0
R R
2 1 0
ICRGF1 ICRGF0
0 0 0
R R R
2 1 0
ICRGR1 ICRGR0
0 0 0
R R R