Renesas H8 Series Hardware Manual page 523

Item Symbol
External clock high t
CPH
width
External clock low t
CPL
width
External clock rise t
CPr
time
External clock fall t
CPf
time
Pin low width t
R E S
REL
Input pin high width t
IH
Input pin low width t
IL
UD pin minimum t
UDH
transition width t
UDL
Notes: 1. Selected with SA1 and SA0 of system control register 2 (SYSCR2).
2. The figure in parentheses applies when an external clock is used.
3. Applies to the HD64F38024R.
4. Applies to the HD64F38024.
Values
Applicable
Pins
Min Typ
OSC 40 —
1
X — 15.26
1
or
13.02
OSC 40 —
1
X — 15.26
1
or
13.02
OSC — —
1
X — —
1
OSC — —
1
X — —
1
10 —
R E S
, , 2 —
I R Q I R Q
0 1
, ,
I R Q I R Q
3 4
IRQAEC,
to
W K P
0
,
W K P
7
TMIC, TMIF,
TMIG,
A D T R G
AEVL, AEVH 0.5 —
, , 2 —
I R Q I R Q
0 1
, ,
I R Q I R Q
3 4
IRQAEC,
to
W K P
0
,
W K P
7
TMIC, TMIF,
TMIG,
A D T R G
AEVL, AEVH 0.5 —
UD 4 —
Section 16 Electrical Characteristics
Max Unit Test Condition
— ns
— µs
— ns
— µs
10 ns
55.0 ns
10 ns
55.0 ns
— t
cyc
— t
cyc
t
subcyc
— t
osc
— t
cyc
t
subcyc
— t
osc
— t
cyc
t
subcyc
Rev. 7.00 Mar 10, 2005 page 481 of 652
Reference
Figure
Figure 16.1
Figure 16.1
Figure 16.1
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.3
Figure 16.6
REJ09B0042-0700