Renesas H8 Series Hardware Manual page 124

Section 3 Exception Handling
Bit 2—IRQAEC Interrupt Enable (IENEC2)
Bit 2 enables or disables IRQAEC interrupt requests.
Bit 2
IENEC2 Description
0 Disables IRQAEC interrupt requests
1 Enables IRQAEC interrupt requests
Bits 1 and 0—IRQ and IRQ
1
Bits 1 and 0 enable or disable IRQ
Bit n
IENn Description
0 Disables interrupt requests from pin
1 Enables interrupt requests from pin
Interrupt Enable Register 2 (IENR2)
Bit 7
IENDT
Initial value 0
Read/Write R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Direct Transfer Interrupt Enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT Description
0 Disables direct transfer interrupt requests
1 Enables direct transfer interrupt requests
Rev. 7.00 Mar 10, 2005 page 82 of 652
REJ09B0042-0700
Interrupt Enable (IEN1 and IEN0)
0
and IRQ interrupt requests.
1 0
I R Q n
6 5
IENAD — IENTG
0 —
R/W W R/W
I R Q n
4 3 2
IENTFH IENTFL
0 0 0
R/W R/W
(initial value)
(initial value)
(n = 1 or 0)
1 0
IENTC IENEC
0 0
R/W R/W
(initial value)