Renesas H8 Series Hardware Manual page 615

RDR—Receive Data Register
Bit 7
RDR7
Initial value 0
Read/Write R
TMA—Timer Mode Register A
Bit 7


Initial value
Read/Write W
6 5
RDR6 RDR5
0 0
R R
Serial receiving data are stored
6 5
 
 
W W
Internal Clock Select
TMA3 TMA2 TMA1
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Appendix B Internal I/O Registers
H'AD
4 3
RDR4 RDR3 RDR2
0 0
R R
H'B0
4 3

TMA3 TMA2
1 0

R/W R/W
Prescaler and Divider Ratio
TMA0 or Overflow Period
φ/8192
0 PSS
φ/4096
1 PSS
φ/2048
0 PSS
φ/512
1 PSS
φ/256
0 PSS
φ/128
1 PSS
φ/32
0 PSS
φ/8
1 PSS
0 PSW 1 s
1 PSW 0.5 s
0 PSW 0.25 s
1 PSW 0.03125 s
0 PSW and TCA are reset
1
0
1
Rev. 7.00 Mar 10, 2005 page 573 of 652
2 1 0
RDR1 RDR0
0 0 0
R R R
Timer A
2 1 0
TMA1 TMA0
0 0 0
R/W R/W
Function
Interval
timer
Clock time
base
(when
using
32.768 kHz)
REJ09B0042-0700
SCI3