Cpu States; Overview - Renesas H8 Series Hardware Manual

Three-state access to on-chip peripheral modules
φ or φ
SUB
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Internal
data bus
(write access)
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
2.7

CPU States

2.7.1

Overview

There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or medium-
speed) mode and subactive mode. In the program halt state there are a sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in
figure 2.14. Figure 2.15 shows the state transitions.
Bus cycle
T state
1
Address
T state
2
Read data
Write data
Rev. 7.00 Mar 10, 2005 page 57 of 652
Section 2 CPU
T state
3
REJ09B0042-0700