Renesas H8 Series Hardware Manual page 11

Item
1.3.1 Pin
Arrangement
Figure 1.4 Pin
Arrangement (TLP-
85V, H8/38024R
Group, H8/38024S
Group)
1.3.2 Pin Functions
Table 1.5 Pin
Functions
2.8.1 Memory Map
Figure 2.16(1)
H8/38024,
H8/38024S, and
H8/38124 Memory
Map
Figure 2.16(3)
H8/38022,
H8/38022S, and
H8/38122 Memory
Map
2.9.1 Notes on Data
Access
Figure 2.17 Data
Size and Number of
States for Access to
and from On-Chip
Peripheral Modules
3.3.2 Interrupt
Control Registers
Interrupt Request
Register 1 (IRR1)
Bit 7
Page Revision (See Manual for Details)
12 Title amended
20, 24 Table amended and note 5 added
Type Symbol
Clock X
1
pins
X
2
5. Does not apply to H8/38124 Group.
61 Figure amended
HD64338024 (mask ROM version)
HD64338024S (mask ROM version)
HD64338124 (mask ROM version)
HD64738024 (PROM version)
63 Figure replaced
67 Notes amended
3. Only the HD64F38024, HD64F38024R, HD64F38122, and HD64F38124 are equipped with
internal I/O registers from H'F020 to H'F02B and on-chip RAM from H'F780 to H'FB7F.
Attempting to access these areas on products other than the HD64F38024, HD64F38024R,
HD64F38122, and HD64F38124 will result in access to an empty area.
85 Table amended
Setting conditions:
When the timer A counter value overflows
Pin No.
FP-80A Pad
No. *
TFP-80C FP-80B TLP-85V
6 8 D3 6
7 9 D2 7
Rev. 7.00 Mar 10, 2005 page xi of xlii
Pad Pad
No. * No. *
1 2 3
I/O Name and Functions
7 6 Input These pins connect to a
32.768-kHz or 38.4-kHz *
8 7 Output
crystal oscillator.
See section 4, Clock
Pulse Generators, for a
typical connection
diagram.
5