Renesas H8 Series Hardware Manual page 580

8-bit single-chip microcomputer
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Appendix A CPU Instruction Set
Mnemonic
MULXU.B Rs, Rd
DIVXU.B Rs, Rd
AND.B #xx:8, Rd
AND.B Rs, Rd
OR.B #xx:8, Rd
OR.B Rs, Rd
XOR.B #xx:8, Rd
XOR.B Rs, Rd
NOT.B Rd
SHAL.B Rd
SHAR.B Rd
SHLL.B Rd
SHLR.B Rd
ROTXL.B Rd
ROTXR.B Rd
Rev. 7.00 Mar 10, 2005 page 538 of 652
REJ09B0042-0700
Operation
B Rd8 × Rs8 → Rd16
B Rd16÷Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
B Rd8∧#xx:8 → Rd8
B Rd8∧Rs8 → Rd8
B Rd8∨#xx:8 → Rd8
B Rd8∨Rs8 → Rd8
B Rd8⊕#xx:8 → Rd8
B Rd8⊕Rs8 → Rd8
B Rd → Rd
B
C
b
b
7
0
B
b
b
7
0
B
C
b
b
7
0
B
0
b
b
7
0
B
C
b
b
7
B
b
b
7
0
Addressing Mode/
Instruction Length (bytes)
2
2
2
2
2
2
2
2
2
2
0
2
C
2
0
2
C
2
0
2
C
Condition Code
I H N Z V C
      14
  (5) (6)   14
 
0  2
 
0  2
 
0  2
 
0  2
 
0  2
 
0  2
 
0  2
 
2
 
0
2
 
0
2
  0
0
2
 
0
2
 
0
2

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