Operation; Power-On Reset Circuit - Renesas H8 Series Hardware Manual

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
14.3

Operation

14.3.1

Power-On Reset Circuit

Figure 14.2 shows the timing of the operation of the power-on reset circuit. As the power-supply
voltage rises, the capacitor which is externally connected to the
the on-chip pull-up resistor (typ. 100 kΩ). Since the state of the
chip, the prescaler S and the entire chip are in their reset states. When the level on the
reaches the specified value, the prescaler S is released from its reset state and it starts counting.
The OVF signal is generated to release the internal reset signal after the prescaler S has counted
131,072 clock (φ) cycles. The noise cancellation circuit of approximately 100 ns is incorporated to
prevent the incorrect operation of the chip by noise on the
To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles
within the specified time. The maximum time required for the power supply to rise and settle after
power has been supplied (t
which is connected to
supply voltage, the power supply circuit should be designed to satisfy the following formula.
(ms) ≤ 80 • C
t
PWON
≤ 3000 ms, C
(t
PWON
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on
the pin is removed. To remove charge on the
R E S
should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a
power-on reset may not occur.
) is determined by the oscillation frequency (f
PWON
pin (C ) . If t
R E S
PWON
R E S
(µF) ± 10/f
OSC
R E S
≥ 0.22 µF, and f
R E S
R E S
R E S
pin.
R E S
means the time required to reach 90 % of power
(MHz)
= 10 in 2-MHz to 10-MHz operation)
OSC
pin, it is recommended that the diode
R E S
Rev. 7.00 Mar 10, 2005 page 443 of 652
pin is gradually charged via
pin is transmitted within the
R E S
) and capacitance
OSC
REJ09B0042-0700
pin