Renesas H8 Series Hardware Manual page 18

Item
9.7.5 Application
Notes
10.2.8 Bit Rate
Register (BRR)
Table 10.3 Examples
of BRR Settings for
Various Bit Rates
(Asynchronous
Mode) (2)
Rev. 7.00 Mar 10, 2005 page xviii of xlii
Page Revision (See Manual for Details)
328 Description amended
2. Use a clock with a frequency of up to 16 MHz for input to the
AEVH and AEVL pins, and ensure that the high and low widths
of the clock are at least half the OSC clock cycle duration. The
duty cycle is immaterial.
329 Description amended
Mode
Watch, subactive, subsleep, standby
φw = 32.768 kHz or 38.4 kHz *
Note: * Does not apply to H8/38124 Group.
349 Table amended
Bit Rate
(bit/s) n
110 3
150 3
200 3
250 3
300 3
600 3
1200 3
2400 3
4800 3
9600 2
19200 2
31250 0
38400 0
Notes amended
1. The value set in BRR is given by the following equation:
N =
(32 • 2
where B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
φ: System clock frequency
n: Baud rate generator input clock number (n = 0, 2, or 3)
(φw/2)
(φw/4)
(φw/8)
φ
10 MHz
Error
N (%)
43 0.88
32 –1.36
23 1.73
19 –2.34
15 1.73
7 1.73
3 1.73
1 1.73
0 1.73
1 1.73
0 1.73
9 0
7 1.73
φ
– 1
2n
• B)
(The relation between n and the clock is shown in table 10.4.)
Maximum AEVH/AEVL Pin Input
Clock Frequency
1000 kHz
500 kHz
250 kHz