Renesas H8 Series Hardware Manual page 81

Notation
Rd
Rs
Rn
(EAd), <EAd>
(EAs), <EAs>
CCR
N
Z
V
C
PC
SP
#IMM
disp
+
–
×
÷
∧
∨
⊕
→
~
:3
:8
:16
( ), < >
General register (destination)
General register (source)
General register
Destination operand
Source operand
Condition code register
N (negative) flag of CCR
Z (zero) flag of CCR
V (overflow) flag of CCR
C (carry) flag of CCR
Program counter
Stack pointer
Immediate data
Displacement
Addition
Subtraction
Multiplication
Division
AND logical
OR logical
Exclusive OR logical
Move
Logical negation (logical complement)
3-bit length
8-bit length
16-bit length
Contents of operand indicated by effective address
Rev. 7.00 Mar 10, 2005 page 39 of 652
Section 2 CPU
REJ09B0042-0700