Renesas H8 Series Hardware Manual page 128

Section 3 Exception Handling
Bits 1 and 0—IRQ and IRQ
1
Bit n
IRRIn Description
0
Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
1 Setting conditions:
When pin
input
Interrupt Request Register 2 (IRR2)
Bit 7
IRRDT
Initial value 0
R/(W) *
Read/Write
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FL, Timer C, or asynchronous event counter
interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is
necessary to write 0 to clear each flag.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7
IRRDT Description
0 Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
1
Setting conditions:
When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in
SYSCR2
Rev. 7.00 Mar 10, 2005 page 86 of 652
REJ09B0042-0700
Interrupt Request Flags (IRRI1 and IRRI0)
0
is designated for interrupt input and the designated signal edge is
I R Q n
6 5

IRRAD

0
R/(W) *
W
4 3
IRRTG IRRTFH IRRTFL
0 0
R/(W) * R/(W) * R/(W) *
(initial value)
(n = 1 or 0)
2 1 0
IRRTC IRREC
0 0 0
R/(W) * R/(W) *
(initial value)