Renesas H8 Series Hardware Manual page 125

Bit 6—A/D Converter Interrupt Enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD Description
0 Disables A/D converter interrupt requests
1 Enables A/D converter interrupt requests
Bit 5—Reserved
Bit 5 is reserved bit: it can only be written with 0.
Bit 4—Timer G Interrupt Enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG Description
0 Disables timer G interrupt requests
1 Enables timer G interrupt requests
Bit 3—Timer FH Interrupt Enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH Description
0 Disables timer FH interrupt requests
1 Enables timer FH interrupt requests
Bit 2—Timer FL Interrupt Enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL Description
0 Disables timer FL interrupt requests
1 Enables timer FL interrupt requests
Section 3 Exception Handling
Rev. 7.00 Mar 10, 2005 page 83 of 652
(initial value)
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REJ09B0042-0700