Renesas H8 Series Hardware Manual page 648

Appendix B Internal I/O Registers
IEGR—IRQ Edge Select Register
Bit 7

Initial value 1

Read/Write
IRQ
0 Falling edge of IRQ
1
Rev. 7.00 Mar 10, 2005 page 606 of 652
REJ09B0042-0700
6 5
 
1 1
 
IRQ
1
0 Falling edge of IRQ
Rising edge of IRQ
1
IRQ Edge Select
3
0 Falling edge of IRQ
Rising edge of IRQ
1
Edge Select
4
, ADTRG pin input is detected
4
Rising edge of IRQ , ADTRG pin input is detected
4
H'F2
4 3
IEG4 IEG3
0 0
R/W R/W
IRQ Edge Select
0
0 Falling edge of IRQ
Rising edge of IRQ
1
Edge Select
, TMIC pin input is detected
1
, TMIC pin input is detected
1
, TMIF pin input is detected
3
, TMIF pin input is detected
3
System Control
2 1 0

IEG1 IEG0

0 0
W R/W R/W
pin input is detected
0
pin input is detected
0