Renesas H8 Series Hardware Manual page 362

Section 9 Timers
Bit 6
OVL Description
0 ECL has not overflowed
Clearing condition:
After reading OVL = 1, cleared by writing 0 to OVL
1 ECL has overflowed
Setting condition:
Set when ECL overflows from H'FF to H'00
Bit 5—Reserved
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Bit 4—Channel Select (CH2)
Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two
independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a
16-bit event counter which is incremented each time an event clock is input to the AEVL pin. In
this case, the overflow signal from ECL is selected as the ECH input clock. When CH2 is set to 1,
ECH and ECL function as independent 8-bit event counters which are incremented each time an
event clock is input to the AEVH or AEVL pin, respectively.
Bit 4
CH2 Description
0 ECH and ECL are used together as a single-channel 16-bit event counter
1 ECH and ECL are used as two independent 8-bit event counter channels
Bit 3—Count-up Enable H (CUEH)
Bit 3 enables event clock input to ECH. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECH value is held. The AEVH pin or the ECL overflow signal can be selected as the event clock
source by bit CH2.
Bit 3
CUEH Description
0 ECH event clock input is disabled
ECH value is held
1 ECH event clock input is enabled
Rev. 7.00 Mar 10, 2005 page 320 of 652
REJ09B0042-0700
(initial value)
(initial value)
(initial value)