Renesas H8 Series Hardware Manual page 371

8-bit single-chip microcomputer

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Active (high-speed), sleep (high-speed)

Active (medium-speed), sleep (medium-speed) (φ/16)

= 1 MHz to 4 MHz

Watch, subactive, subsleep, standby

φw = 32.768 kHz or 38.4 kHz *

Note: * Does not apply to H8/38124 Group.

3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR.

Or, set CUEH and CRCH simultaneously before inputting the clock. After that, do not change

the CUEH value while using in the 16-bit mode. Otherwise, an error counter increment may

occur. Also, to reset the counter, clear CRCH and CRCL to 0 simultaneously or clear CRCL

and CRCH to 0 sequentially, in that order.

4. When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH,

ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.

When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in

AEGSR before modifying these registers.

5. The event counter PWM data register and event counter PWM compare register must be set so

that event counter PWM data register < event counter PWM compare register. If the settings

do not satisfy this condition, do not set ECPWME to 1 in AEGSR.

6. As synchronization is established internally when an IRQAEC interrupt is generated, a

maximum error of 1 t

will occur between clock halting and interrupt acceptance.

Maximum AEVH/AEVL Pin Input

Clock Frequency

Rev. 7.00 Mar 10, 2005 page 329 of 652

Section 9 Timers

REJ09B0042-0700