Renesas H8 Series Hardware Manual page 602

Appendix B Internal I/O Registers
LVDSR—Low-Voltage Detection Status Register
Note: This register is implemented on the H8/38124 Group only.
Bit 7
OVF
0 *
Initial value
Read/Write R/W
LVD Reference Voltage Stabilized Flag
0 [Clearing condition]
1 [Setting condition]
Note: * These bits initialized by resets trigged by LVDR.
Rev. 7.00 Mar 10, 2005 page 560 of 652
REJ09B0042-0700
6 5
 
0 0
R/W R/W
LVD Power Supply Voltage Drop Flag
0 [Clearing condition]
When 0 is written after reading 1
1 [Setting condition]
When the power supply voltage drops below Vint(D)
Reference Voltage External Input Select
0 The on-chip circuit is used to generate the reference
voltage
1 The reference voltage is input to the Vref pin from
an external source
When 0 is written after reading 1
When the low-voltage detection counter (LVDCNT) overflows
H'87
4 3

VREFSEL
0 0
R/W R/W R/W
LVD Power Supply Voltage Rise Flag
0 [Clearing condition]
When 0 is written after reading 1
1 [Setting condition]
When the power supply voltage drops below
Vint(D) while the LVDUE bit in LVDCR is set
to 1, and it rises above Vint(U) before
dropping below Vreset1
2 1 0

LVDDF LVDUF
0 * 0 *
0
R/W R/W
(initial v alue)
(initial value)
(initial value)
(initial value)
LVDC