Renesas H8 Series Hardware Manual page 38

10.2.5 Serial Mode Register (SMR) ............................................................................... 337
10.2.6 Serial Control Register 3 (SCR3) ........................................................................ 340
10.2.7 Serial Status Register (SSR) ................................................................................ 344
10.2.8 Bit Rate Register (BRR) ...................................................................................... 348
10.2.9 Clock stop register 1 (CKSTPR1) ....................................................................... 354
10.2.10 Serial Port Control Register (SPCR).................................................................... 354
10.3 Operation .......................................................................................................................... 356
10.3.1 Overview.............................................................................................................. 356
10.3.2 Operation in Asynchronous Mode ....................................................................... 360
10.3.3 Operation in Synchronous Mode ......................................................................... 369
10.3.4 Multiprocessor Communication Function ........................................................... 376
10.4 Interrupts........................................................................................................................... 383
10.5 Application Notes ............................................................................................................. 384
Section 11 10-Bit PWM
11.1 Overview........................................................................................................................... 389
11.1.1 Features................................................................................................................ 389
11.1.2 Block Diagram..................................................................................................... 390
11.1.3 Pin Configuration ................................................................................................ 391
11.1.4 Register Configuration......................................................................................... 392
11.2 Register Descriptions........................................................................................................ 392
11.2.1 PWM Control Register (PWCRm) ...................................................................... 392
11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm) ..................................... 394
11.2.3 Clock Stop Register 2 (CKSTPR2) ..................................................................... 395
11.3 Operation .......................................................................................................................... 396
11.3.1 Operation ............................................................................................................. 396
11.3.2 PWM Operation Modes....................................................................................... 397
Section 12 A/D Converter
12.1 Overview........................................................................................................................... 399
12.1.1 Features................................................................................................................ 399
12.1.2 Block Diagram..................................................................................................... 400
12.1.3 Pin Configuration ................................................................................................ 401
12.1.4 Register Configuration......................................................................................... 401
12.2 Register Descriptions........................................................................................................ 402
12.2.1 A/D Result Registers (ADRRH, ADRRL) .......................................................... 402
12.2.2 A/D Mode Register (AMR) ................................................................................. 402
12.2.3 A/D Start Register (ADSR) ................................................................................. 404
12.2.4 Clock Stop Register 1 (CKSTPR1) ..................................................................... 405
12.3 Operation .......................................................................................................................... 406
Rev. 7.00 Mar 10, 2005 page xxxviii of xlii
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