Notes On Rewriting Port Mode Registers - Renesas H8 Series Hardware Manual

3.4.2

Notes on Rewriting Port Mode Registers

When a port mode register is rewritten to switch the functions of external interrupt pins and when
the value of ECPWME in AEGSR is rewritten to switch between selection/non-selection of
IRQAEC, the following points should be observed.
When an external interrupt pin function is switched by rewriting the port mode register that
controls pins ,
I R Q I R Q
4
the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear
the interrupt request flag to 0 after switching pin functions. When the value of ECPWME in
AEGSR that sets selection/non-selection of IRQAEC is rewritten, the interrupt request flag may
be set to 1, even if a valid edge has not arrived on the selected IRQAEC or IECPWM (PWM
output for AEC). Therefore, be sure to clear the interrupt request flag to 0 after switching the pin
function. Table 3.5 shows the conditions under which interrupt request flags are set to 1 in this
way.
Table 3.5 Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1
IRR1 IRRI4
IRRI3
IRREC2
IRRI1
IRRI0
, , ,
I R Q I R Q W K P
3 1 0
Conditions
When PMR1 bit IRQ4 is changed from 0 to 1 while pin
IEG4 = 0.
When PMR1 bit IRQ4 is changed from 1 to 0 while pin
IEG4 = 1.
When PMR1 bit IRQ3 is changed from 0 to 1 while pin
IEG3 = 0.
When PMR1 bit IRQ3 is changed from 1 to 0 while pin
IEG3 = 1.
When an edge as designated by AIEGS1 and AIEGS0 in AEGSR is detected
because the values on the IRQAEC pin and of IECPWM at switching are different
(e.g., when the rising edge has been selected and ECPWME in AEGSR is changed
from 1 to 0 while pin IRQAEC is low and IECPWM = 1).
When PMRB bit IRQ1 is changed from 0 to 1 while pin
IEG1 = 0.
When PMRB bit IRQ1 is changed from 1 to 0 while pin
IEG1 = 1.
When PMR2 bit IRQ0 is changed from 0 to 1 while pin
IEG0 = 0.
When PMR2 bit IRQ0 is changed from 1 to 0 while pin
IEG0 = 1.
to , the interrupt request flag may be set to 1 at
W K P
7 0
Rev. 7.00 Mar 10, 2005 page 99 of 652
Section 3 Exception Handling
is low and IEGR bit
4
I R Q
is low and IEGR bit
4
I R Q
is low and IEGR bit
3
I R Q
is low and IEGR bit
3
I R Q
is low and IEGR bit
1
I R Q
is low and IEGR bit
1
I R Q
is low and IEGR bit
0
I R Q
is low and IEGR bit
0
I R Q
REJ09B0042-0700