Minimum Board Stack-Up Configuration Used For Signal Integrity; Pxa27X Processor Memory Clock And Sdcas Routing Topology - Intel PXA27 Series Design Manual

System Memory Interface
See Figure 6-3
Figure 6-3. PXA27x Processor Memory Clock and SDCAS Routing Topology
Series Series Series
termination termination termination
Bulverde Bulverde Bulverde
PXA27x PXA27x PXA27x
Series Series Series
termination termination termination
Bulverde Bulverde Bulverde
PXA27x PXA27x PXA27x
6.4.1.3

Minimum Board Stack-up Configuration used for Signal Integrity

Information in
analysis. Refer to
on board stack-up.
Figure 6-4. Minimum Board Stack-up Configuration used for Signal Integrity
Note
•Mask Thickness = 0.2mils +/- 0.1
•Mask Er = 3.65
µ-strips become buried when HDI is
deposited and have no solder mask
3 mils +/- 1 width & E2E space
HDI
HDI Insulator 2 mils +/- 1 Er = 4.15 +/- 0.55
Preg Er = 4.15 +/- 0.55
Plane = 0.7 mils +/- 0.2 (031);
Pre Preg Er = 4.15 +/- 0.55
Core Er = 4.15 +/- 0.55
II:6-8
for the recommended value for the 20 Ω + 5% series termination.
L1 L1 L1
SDRAM SDRAM SDRAM
L1 L1 L1 L2 L2 L2
SDRAM SDRAM SDRAM
Figure 6-4 indicates the board stack-up configuration used for signal integrity
Part I: Section 2.2.1, "PCB Layer Assignment (Stackup),"
HDI
1.4 +/- 0.2 mils (062)
4 mils +/- 2
(031, 062)
5 mils +/- 1.5 width & E2E space (031, 062)
L2 L2 L2 L2 L2 L2
SDRAM SDRAM SDRAM
Series Series Series
termination termination termination
Bulverde Bulverde Bulverde
PXA27x PXA27x PXA27x
SDRAM SDRAM SDRAM
HDI thick = 1.45 mils +/- 0.55 thick (062)
HDI thick = 0.87 mils +/- 0.28 thick (031)
µ - bµ µ - bµ
5 mils +/- 1.5 width & E2E space (031, 062)
0.7 mils +/- 0.2 thick (031)
Strip 1.4 mils +/- 0.2 thick (062)
®
Intel PXA27x Processor Design Guide
L2 L2 L2
SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
L1 L1 L1
SDRAM SDRAM SDRAM
for recommendation
µ/Bµ = 1.45 mils +/- 0.55 thick (062)
µ/Bµ = 1.00 mils +/- 0.28 thick (031)
Preg = 4
mils +/- 2