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IXP28XX Network Processor
QDR SRAM
Table 20.
4.5.3
Figure 30.
68
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Table 20
lists the QDR address stack-up signal cross-section details.
QDR Address Stack-up Signal Cross-section Details
Trace
QDR
Parameter
Width (W)
Signal
[mils]
Main
Trunk = 10
Value
Address
Branches
= 3.5
QDR SRAM D (Data Out) Topology
For Data Bus to work successfully at 233MHz only x9 SRAM parts need to be used and not x18
parts for multiple loads applications. Thus the data bus (READ and WRITE) should be split in two
halves each with a 9bit including the parity bit. The loads for each Data signal must be maintained
at 2 SRAMs only that are clam-shelled together so that they electrically constitute one load only.
As mentioned in section 3 on SRAM clam-shelling, some signals are not fully mirrored in the
SRAM part. Data-OUT is an example of these un-mirrored signals. Therefore, for Data-OUT
signals a daisy-chain configuration would be used for its topology. A better choice, however, is to
use a T-topology for Data-OUT whenever it is possible.
Figure 30
illustrates the routing topology for QDR SRAM D (Data Out).
D (Data Out) Routing Topology
Daisy-Chained
Data-Out (D0 - D7, D9 - D16)
and Parity-Out (D8, D17)
Signals
®
Intel
IXP2800 Driver
Data-Out, Parity-Out
Table 21
provides routing guidelines for the QDR D signal group.
Trace
D1
Trace
Thickness
Thickness
Spacing
(Tsignal)
(TD1)
(S) [mils]
[mils]
[mils]
0.5
15 - 20
5.0
V
= 0.75V
TT
Ω
R
= 50
TT
D
A
B
Spacing
D2
between
Thickness
Er(D1) Er(D2)
signal
(Td2)
groups
[mils]
[mils]
5.7
3.5
3.8
20 - 25
Top
SRAM
Bottom
SRAM
C
B3954-01
Hardware Design Guide
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