Data Bus Topology; Figure 46. Data Signal Routing Topology - Intel 852GM Design Manual

System Memory Design Guidelines (DDR-SDRAM)
7.3.4.1.

Data Bus Topology

Figure 46. Data Signal Routing Topology

G M C H
G M C H
D ie
The data signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within the
DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-DDR
related signals. Data signals should be routed on inner layers with minimized external trace lengths.
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L1
P 1
SO -D IM M 0 PA D
L2 L3
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Intel 852GM Chipset Platform Design Guide
R
V tt
R t
L4
SO -D IM M 1 PA D