Ddr Sdram Vdd Decoupling; Ddr Vtt Decoupling Placement And Layout Guidelines; Ddr Memory Power Delivery Design Guidelines - Intel 852GM Design Manual

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12.5.2.2.

DDR SDRAM VDD Decoupling

Discontinuities in the DDR signal return paths will occur when the signals transition between the
motherboard and the SO-DIMMs. To account for this ground to 2.5-V discontinuity, a minimum of nine
0603 form factor 0.1-µF high frequency bypass capacitors is required between the SO-DIMMs to help
minimize any anticipated return path discontinuities that will be created. The capacitors should be
distributed as evenly as possible between the two SO-DIMMs.
• Wide ground trace from each capacitor should be connect to a via that transitions to the ground plane.
Each ground via should be placed as close to the ground pad as possible.
• Wide 2.5-V trace from each capacitor should connect to a via that transitions to the 2.5-V copper
flood. Each via should be placed as close to the capacitor pad as possible. Each capacitor pad should
also connect to the closet 2.5-V SO-DIMM pin on either the first or second SO-DIMM connector
with a wide trace.
12.5.2.3.

DDR VTT Decoupling Placement and Layout Guidelines

The VTT termination rail must be decoupled using high-speed bypass capacitors, one, 0603 form factor,
0.1-µF capacitor and one, 0603 form factor, 0.01-µF capacitor per four DDR signals. They must be
place more than 100 mils from the termination resistors.
• A VTT copper flood must be used. The decoupling capacitors must be spread out across the
termination island so that all the parallel termination resistors are near high frequency capacitors.
• Each capacitor ground via should be as close to the capacitor pad as possible, within 25 mils with
as thick a trace as possible.
12.5.3.

DDR Memory Power Delivery Design Guidelines

The main focus of these GMCH guidelines is to minimize signal integrity problems and improve the
power delivery to the GMCH system memory interface and the DDR memory SO-DIMMs. This section
discusses the DDR memory system voltage and current requirements as of publishing for this document.
This document is not the original source for these specifications. Figure 123 shows the implementation
2.5 V, 1.25 V and SMVREF on the CRB only as an example. It is the responsibility of the system
designer to ensure that the power requirements for the DDR and GMCH are met. Refer to the following
documents for the latest details on voltage and current requirements found in this design guide.
• JEDEC Standard, JESD79 (Release 2), Double Data Rate (DDR) SDRAM Specification
• Intel DDR 266 JEDEC Spec Addendum Rev 1.0 or later
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Intel 852GM Chipset Platform Design Guide
Intel 852GM Platform Power Delivery Guidelines
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