Figure 105. Decoupling Capacitors Placement And Connectivity - Intel 852GME Design Manual

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Figure 105. Decoupling Capacitors Placement and Connectivity

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Intel 852GME, Intel 852GMV and Intel
VddA
XTAL_Out
C1
Vs
s
Vdd
C2
Vss
Vdd
C3
Vss
Vdd
66Buff0
/ 3V66_2
VddA
®
852PM Chipset Platforms Design Guide
Platform Power Delivery Guidelines
REF
1 56
Vdd
0
S1
2 55
XTAL_In
S0
3 54
CPU_Sto
4
53
Vss
p #
CPU
5 52
PCIF 0
0
CPU
6 51
PCIF 1
/0
7 50
PCIF 2 Vdd
CPU
8 49
Vdd
1
CPU
9
48
Vss
/1
47
10
PCI 0 Vss
11 46
PCI 1 Vdd
CPU
45
PCI 2
2
12
CPU
13 44
PCI 3
/2
Mult
14
43
Vdd
0
IRE
Vs
15 42
Vss
F
s
Gr
41
ou
16
PCI 4 Vss Iref
nd
Flo
S2
od
17 40
PCI 5
US
39
B 48
18
PCI 6
MHz
DO
T 48
19 38
Vdd
MHz
20
Vdd
37
Vss
48 MHz
36
Vss
21
48 MHz
66Buf
3V66_1 /
f1 /
22 35
VCH
3V66_
3 66Buf
PCI_Sto
f2 /
23 34
p #
3V66_
4
66In /
3V66
24 33
3V66_5
_0
SCL
PWRD Vd
25 32 Vss Vdd
K
WN# d
Vdd
31
Vs
26
A
s
Vss SCL
27
30
A K
SDAT
Vtt_Pwr
28 29
A
gd #
Vss Plane Vias
C6
Vss
Vdd
C5
Vss
Vdd
VddA
C4
Vss
Vdd
225