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5.0
High-Speed Design Concerns
This chapter describes basic high-speed design practices as they apply to the EP80579.
5.1
Return Path
The return path is the route current takes to return to its source. It may take a path
through ground planes, power planes, other signals, or integrated circuits. The return
path is based on electromagnetic field effects. It is useful to think of the return path as
the path of least impedance nearest the signal conductor. Discontinuities in the return
path often have signal integrity and timing effects similar to the discontinuities in the
signal conductor. Therefore, the return paths must be given similar considerations. A
simple way to evaluate return path parasitic inductance is to draw a loop that traces the
current from the driver through the signal conductor, to the receiver, and then back
through the ground/power plane to the driver again. The smaller the area of the loop,
the lower the parasitic inductance.
The following set of rules for the return path apply to all designs:
• Always trace out the return current path and pay as much attention to the return
path as to the path of the signal conductor.
• Do not allow splits in the reference planes in the path of the return current.
• Do not route signals on the reference planes near the system bus signals.
• Do not allow signal layer changes that force the return path to make a reference
plane change, even when from one ground layer to another ground layer.
• Decoupling capacitors do not adequately compensate for a plane split.
• Do not route over via anti-pads or socket anti-pads.
When reference plane changes must be made:
• Change from a ground reference to a ground reference and place a via that
connects the two planes as close as possible to the signal via. This guideline also
applies when making a change from VCC to VCC.
• For symmetric stripline, provide return path vias for both ground and VCC.
• Do not switch the reference from VCC to ground or ground to VCC.
5.2
Decoupling Theory
The primary objective of the decoupling guidelines is to minimize the impact of return
path discontinuities and to ensure that the I/O has adequate power decoupling. The
worst-case return path discontinuity anticipated is for systems that use microstrip
structures on the motherboard. When a motherboard uses symmetric stripline with
VCC and ground references, a discontinuity does not exist and additional decoupling is
not necessary. When the motherboard routing references only a single VCC or ground
plane, a return path discontinuity exists.
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
40
®
Intel
EP80579 Integrated Processor Product Line—High-Speed Design Concerns
May 2010
Order Number: 320068-005US
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