Bulk Decoupling; High-Frequency Decoupling; Proper Decoupling Capacitor Placement With Respect To Vias - Intel Pentium M Processor Design Manual

® ®
Intel Pentium M Processor and Intel
High-Speed Design Concerns
The inductance of the system due to cables and power planes slows the power supply's ability to
respond quickly to a current transient. Decoupling a power plane may be broken into several
independent parts. The closer to the load the capacitor is placed, the more inductance is bypassed.
By bypassing the inductance of leads, power planes etc., less capacitance is required. However,
closer to the load there is less room for capacitance. Therefore, trade-offs must be made.
12.2.1

Bulk Decoupling

Larger bulk storage components, such as electrolytic capacitors, supply current during longer
lasting changes in current demand by the component, such as coming out of an idle condition.
Similarly, they act as a storage well for current when entering an idle condition from a running
condition.
Power bypassing is required due to the relatively slow speed at which a DC-to-DC converter may
react. Bulk capacitance supplies energy from the time the high-frequency decoupling capacitors are
drained, until the power supply may react to the demand. More correctly, the bulk capacitors in the
system slow the transient requirement seen by the power source to a rate it is able to supply, while
the high-frequency capacitors slow the transient requirement seen by the bulk capacitors to a rate
they may supply.
Maintaining voltage tolerance during changes in current requires high-density bulk capacitors with
low Effective Series Resistance (ESR), and low Effective Series Inductance (ESL). Use thorough
analysis when choosing these components.
12.2.2

High-Frequency Decoupling

The system boards should include high-frequency capacitors as close to the load power and ground
pins as possible. Place as many capacitors as possible in the load cut out area.
In addition, high-frequency decoupling may be required for signal integrity. For systems using
microstrip configurations, a return path discontinuity may exist due to the baseboard traces having
only one reference plane.
Place high-frequency decoupling as close to the power pins of the load as physically possible. Use
both sides of the board when necessary for placing load to achieve the optimum proximity to the
power pins. This is vital because the inductance of the board's metal plane layers could cancel the
usefulness of these low inductance components.
Shorten the path from the capacitor pads to the pins the capacitor is decoupling. When possible,
place the vias connecting to the planes within the pad of the capacitor. When this is not possible,
keep the traces as short and wide as is feasible. Possibly one or both ends of the capacitor may be
connected directly to the pins of the load without the use of a via.
concepts.
Figure 147. Proper Decoupling Capacitor Placement with Respect to Vias
Unacceptable
Via
216
®
E7501 Chipset Platform
Good
Bad
Pad
Figure 147 illustrates these
Better
Pin Capacitors
Design Guide
Optimal