Gmch Vccsm Decoupling; Ddr Memory Device Vdd Decoupling; Ddr Vtt Decoupling Placement And Layout Guidelines; Ddr Memory Power Delivery Design Guidelines - Intel 855GM Design Manual

Intel 855GM/GME Chipset Based System Power Delivery Guidelines
13.5.1.1.

GMCH VCCSM Decoupling

For the VCCSM pins of the GMCH, a minimum of eleven, 0603 form factor, 0.1-µF, high frequency
capacitors is required and must be placed within 150 mils of the GMCH package. The capacitors should
be evenly distributed along the GMCH DDR system memory interface and must be placed perpendicular
to the GMCH with the power (2.5 V) side of the capacitors facing the GMCH.
• Every GMCH ground and VCCSM power ball in the system memory interface should have its own
via.
• Each capacitor should also have its own 2.5-V via within 25 mils of the capacitor pad for
connecting to a 2.5-V copper flood. The traces from the capacitors should also be wide and connect
to the outer row of balls on the GMCH.
• The ground end of each capacitor must connect to the ground flood and to the ground plane
through a via. Each via should be as close to the associated capacitor pad as possible, within 25
mils and with as thick a trace as possible.
13.5.1.2.

DDR Memory Device VDD Decoupling

Discontinuities in the DDR signal return paths will occur when the signals transition between the
motherboard and the SO-DIMMs. To account for this ground to 2.5-V discontinuity, a minimum of nine
0603 form factor 0.1-µF high frequency bypass capacitors is required between the SO-DIMMs to help
minimize any anticipated return path discontinuities that will be created. The capacitors should be
distributed as evenly as possible between the two SO-DIMMs.
• A wide ground trace from each capacitor should be connect to a via that transitions to the ground
plane. Each ground via should be placed as close to the ground pad as possible.
• A wide 2.5-V trace from each capacitor should connect to a via that transitions to the 2.5-V copper
flood. Each via should be placed as close to the capacitor pad as possible. Each capacitor pad
should also connect to the closet 2.5-V SO-DIMM pin on either the first or second SO-DIMM
connector with a wide trace.
13.5.1.3.

DDR VTT Decoupling Placement and Layout Guidelines

The VTT termination rail must be decoupled using high-speed bypass capacitors, one 0603 form factor
0.1-µF capacitor and one 0603 form factor 0.01-µF capacitor per four DDR signals.
• A VTT copper flood must be used. The decoupling capacitors must be spread out across the
termination island so that all the parallel termination resistors are near high frequency capacitors.
• Each capacitor ground via should be as close to the capacitor pad as possible, within 25 mils with
as thick a trace as possible.
13.5.2.

DDR Memory Power Delivery Design Guidelines

The main focus of these GMCH guidelines is to minimize signal integrity problems and improve the
power delivery to the GMCH system memory interface and the DDR memory SO-DIMMs. This section
discusses the DDR memory system voltage and current requirements as of publishing for this document.
This document is not the original source for these specifications. Figure 139 shows the implementation
2.5 V, 1.25 V and SMVREF on the CRB only as an example. It is the responsibility of the system
designer to ensure that the power requirements for the DDR and GMCH are met. Refer to the following
documents for the latest details on voltage and current requirements found in this design guide.
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Intel 855GM/855GME Chipset Platform Design Guide
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