Communication Prescaler Control Register (Cdcr0/1); Table 12-8 Communication Prescaler - Fujitsu MB90420/5 (A) Series Hardware Manual

12.4.5 Communication Prescaler Control Register (CDCR0/1)

The communication prescaler control register (CDCR0/1) controls the division of the machine clock.
n Communication prescaler control register (CDCR0/1)
The operation clock for the UART is obtained by dividing the machine clock. The UART is designed to
obtain a regular baud rate for various machine clock cycles by this communication prescaler. The output of
this communications prescaler is also used as the operation clock for the expansion I/O serial interface. The
bit configuration of the CDCR0/1 is shown below:
Address
CDCR0: 00003D
H
CDCR1: 00003F
H
[bit 15] MD (Machine clock Divide mode select)
This bit is the operation enable bit for the communication prescaler.
0: The communication prescaler stops.
1: The communication prescaler operates.
[bits 11 to 8] DIV3 to DIV0 (DIVide 3 to 0)
The clock division ratio of the machine clock is determined according to Table 12-8.
Note: When the clock division ratio is changed, allow two clock cycles as the clock stabilization wait time
before communications.
bit 15 bit 14 bit 13
— —
MD
R/W

Table 12-8 Communication Prescaler

MD DIV3 DIV2
0 — —
1 0 0
1 0 0
1 0 0
1 0 0
1 0 1
1 0 1
1 0 1
1 0 1
UART
bit 12 bit 11 bit 10
—
DIV3 DIV2
R/W R/W
DIV1 DIV0
— —
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
12-17
bit 9 bit 8
DIV1 DIV0 Initial value
R/W R/W 0 - - - 0000
div
Stop
1
2
3
4
5
6
7
8
B