Lin-Uart Extended Communication Control Register (Eccr) - Fujitsu MB95630H Series Hardware Manual

MB95630H Series
14.7.6 LIN-UART Extended Communication Control
Register (ECCR)
The LIN-UART extended communication control register (ECCR) is used for the
bus idle detection, the synchronous clock setting, and the LIN synch break
generation.
■ Register Configuration
bit 7
Field Reserved
Attribute W
Initial value 0
■ Register Functions
[bit7] Reserved bit
Always set this bit to "0".
[bit6] LBR: LIN synch break generation bit
In operating mode 3, if this bit is set to "1", a LIN synch break whose length is specified in the LBL[1:0] bits
in the ESCR register is generated.
In operating mode 0/1/2, set this bit to "0".
bit6
Read access
Writing "0"
Writing "1"
[bit5] MS: Transmission side/reception side of serial clock select bit
This bit selects the transmission side/reception side of the serial clock in operating mode 2.
If the transmission side (MS = 0) is selected, the LIN-UART generates a synchronous clock.
If the reception side (MS = 1) is selected, the LIN-UART receives an external serial clock. In mode 0/1/3,
this bit is fixed at "0".
Modify this bit only when the SCR:TXE bit is "0".
bit5
Writing "0"
Writing "1"
Note: When the reception side is selected, the external clock must be selected as the clock source and the
external clock and the external clock input must be enabled (SMR:SCKE = 0, EXT = 1, OTO = 1).
MN702-00009-1v0-E
6 5
LBR MS
W R/W
0 0
The read value is always "0".
Has no effect on operation.
Generates a LIN synch break.
Selects the transmission side (serial clock generation).
Selects the reception side (external serial clock reception).
FUJITSU SEMICONDUCTOR LIMITED
4 3
SCDE SSM
R/W R/W
0 0
Details (only for operating mode 3)
Details (only for operating mode 2)
CHAPTER 14 LIN-UART
14.7 Registers
2 1
Reserved RBI
W R
0 X
0
TBI
R
X
255