Keithley 4200-SCS Reference Manual page 1659

Semiconductor characterization system
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Model 4200-SCS Reference Manual
NOTE:
Figure M-14
Detailed J-ramp flow diagram
*Force
V
use
*Measure
*I
use
?
No
Force
I
init
Measure
V
<
init
?
No
V
=
prev
Q
bd
I
=
stress
*Optional
Note: All values are absolute – no (+) or (-) signs have been incorporated.
4200-901-01 Rev. S / May 2017
The following diagram from JESD35-A has been reproduced with permission from
JEDEC. This flowchart is JEDEC copyright protected material.
I
use
Initial Failure Class A
Stop Test – TYPE 0
I
>
init
Initial Failure Class B
Stop Test – TYPE 1
I
Force
Measure
V
meas
.85 to .95 *
V
init
?
No
V
use
V
prev
Q
Q
=
+
bd
bd
V
Q
Q
=
meas
bd
Voltage/Current
0
=
Compliance
F
I
?
*
init
No
I
I
=
stress
Return to
Force
Measure
V
stress
V
Non-Catastrophic Failure
Stop Test – Type 4
<
V
Yes
prev
Force
Measure
V
=
meas
T
I
*
interval
stress
V
or
meas
Yes
F
*
stress
Other Failure
Stop Test – Type 5
Section Topics
I
init
V
Catastrophic Failure
Stop Test – Type 2
V
<
Yes
meas
init
Test Successfully
?
Completed
No
V
q
bd
I
init
Optionally Record:
V
V
Catastrophic
<
meas
use
Yes
Failure - Stop Test
?
No
Optional Type 5
Classification
5.1 Q
5.2 Reached Current
Compliance
5.3 Reached Voltage
Compliance
Appendix M: WLR Testing
Record
V
=
bd
prev
Q
=
/area
bd
Type 2
V
init
I
use
I
bd
Masked
Type 3
Q
bd
max
M-17

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