Keithley 4200-SCS Reference Manual page 1656

Appendix M: WLR Testing
J-ramp test: qbd_rmpj User Module
The J-ramp test is performed by the Ramp-J UTM in the Qbd Project Plan, which is shown in
Figure M-9. This test uses the qbd_rmpj User Module of the wlrlib User Library and is documented
as follows:
User Module description
Performs a Charge-to-Breakdown test using the QBD J-ramp test algorithm described in JESD35-
A "Procedure for Wafer Level Testing of Thin Dielectrics." This algorithm forces a logarithmic
current ramp until the oxide layer breaks down. This algorithm is capable of a maximum current of
+/- 1A if a high power SMU is used. The flow diagram for the V-ramp test is shown in
Figure M-13
Syntax
status =
Technique
See JEDEC standard JESD35-A "Procedure for Wafer-Level-Testing of Thin Dielectrics,"
referenced in
NOTE:
M-14
shows the default parameters for the qbd_rmpj User Module.
qbd_rmpj(int hi_pin, int lo_pin1, int lo_pin2, int lo_pin3, char *HiSMUId, char
*LoSMUId1, char *LoSMUId2, char *LoSMUId3, double v_use, double I_init,
double I_start, double F, int t_step, double exit_volt_mult, double I_max, double
q_max, double area, double *V_stress, int V_size, double *I_stress, int I_size,
double *T_stress, int T_size, double *q_stress, int q_size, double *Q_bd, double
*q_bd, double *v_bd, double *I_bd, double *t_bd, int *failure_mode, int
*test_status)
Appendix L.
Some of the descriptions of the following Input Variables and Output Variables are
quoted from the JESD35-A standard. The variables quoted from the standard
include this reference identification: (Ref. JESD35-A).
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Figure M-14.
4200-901-01 Rev. S / May 2017