Keithley 4200-SCS Reference Manual page 1645

Model 4200-SCS Reference Manual
HCI degradation: Background information
Hot Carrier Injection (HCI) degradation is one of the most important device issues facing the
semiconductor industry. Small gate length and process variations in today's semiconductor
process can result in dramatic degradation in HCI device performance. In the last few years HCI
lifetimes have reduced dramatically. In some cases, drive current lifetimes have dropped from
years to weeks. HCI effects are enhanced with device scaling (this includes a reduction in device
gate length). This means that HCI effects will be an even greater concern in the future. HCI is
clearly an important semiconductor issue and the need to monitor HCI on a regular basis is a
critical test requirement.
Hot carrier damage occurs in MOS devices when carriers (electrons or holes) are accelerated in
the channel. In short channel devices, these electrons/holes attain velocities high enough to cause
impact ionization. Impact ionization, in turn, creates extra carriers in the MOS channel. These
extra carriers result in significant substrate currents and in some cases attain high enough energy
to overcome the semiconductor-oxide barrier and are trapped in the oxide. Most of the oxide
carrier trapping occurs at the drain edge where carrier velocity is maximized. These trapped
channel electrons can cause significant device performance asymmetry and shifts in critical device
parameters such as threshold voltage and device drive current. In some cases, as much as 10%
change in measured device parameters can occur within a few days.
Today's devices are becoming increasingly susceptible to Hot Carrier effects. In the past, the linear
drain current target value for successful hot carrier device performance was a 10% change in 10
years. Typically, today's manufactured devices can no longer meet this specification and as much
as 10% degradation in linear drain current can occur in a few days. Because of this fact, the
semiconductor manufacturer has even a greater need to monitor HCI effects.
HCI and WLR project plans
There are five 4200-SCS project plans for HCI and WLR testing: HCI_1_DUT, HCI_4_DUT,
NBTI_1_DUT, EM_const_I, and Qbd.
All but the Qbd project plans use Subsite Cycling in the Stress/Measure Mode. For details, see
Subsite cycling
Each of these five projects can be used as configured or modified as needed for your testing
requirements.
HCI_1_DUT and HCI_4_DUT project plans
The HCI_1_DUT project plan is shown in
subsite cycling using voltage stressing on the single n-channel MOSFET device (4terminal-n-fet).
After the first pre-stress cycle to perform characterization tests, subsequent cycles voltage stress
the device for a specified period of time before again performing the tests. The Device Stress
Properties setup window for the HCI_1_DUT project is shown in
The HCI_4_DUT project plan is similar to the HCI_1_DUT project plan except it is configured to
test four devices using a switching matrix for connections.
In a parallel connection scheme, up to 20 devices can be stressed by voltage.
an example of twenty parallel-connected devices being stressed by eight gate and drain voltages.
4200-901-01 Rev. S / May 2017
in Section 6.
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Figure M-1. The subsite plan (HC) is configured for
Figure
Appendix M: WLR Testing
M-2.
Figure M-3 shows
M-3