Keithley 4200-SCS Reference Manual page 1649

Model 4200-SCS Reference Manual
Figure M-8
EM test: Eight devices being current stressed by eight SMUs
Qbd project plan
The Qbd project plan includes UTMs for the Ramp-V test and the Ramp-J test. These tests adhere
to the JESD35-A standard procedures for wafer-level-testing of thin dielectrics. This project (see
Figure
Details on the these tests, including the User Modules (input and output variables) for the UTMs,
are covered in
Figure M-9
Qbd project
Configuration sequence for subsite cycling
There are four Project Plans that use subsite cycling. These include HCI_1_DUT, HCI_4_DUT,
NBTI_1_DUT, and EM_const_I. The process flow for these projects is shown in
NOTE:
When adding a device plan or test to a subsite cycling project, the following sequence must be
followed:
1.
2.
3.
4200-901-01 Rev. S / May 2017
SMU1
GNDU
SMU5
M-9) does not use subsite cycling.
V-ramp and J-ramp tests
A new project plan for subsite cycling can be created or one of the four existing
project plans can be modified as needed. For details, see
deleting a Project Plan
Insert a Device Plan for the type of device to be tested. For example, if testing a 4-terminal,
n-channel MOSFET, insert the 4terminal-n-fet device into the subsite plan.
Under the Device Plan, insert a new test (ITM or UTM) or copy a test from the test library
and make the proper modifications.
Use the Formulator for the ITM or UTM to configure data calculations on test data. The
window to set the formulator is opened by clicking the Formulator button on the Definition
tab of the ITM or UTM. For details, see
Section 6.
Return to
SMU2 SMU3
SMU6 SMU7
later in this appendix.
in Section 6.
Analyzing test data using the Formulator
Section Topics
Appendix M: WLR Testing
SMU4
SMU8
Figure
Building, modifying, and
M-10.
in
M-7