Keithley 4200-SCS Reference Manual page 1655

Semiconductor characterization system
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Model 4200-SCS Reference Manual
NOTE:
NOTE:
Figure M-12
Detailed V-ramp flow diagram
V
maximum or comp.
Optional
Q
Q
=
bd
V
=
prev
V
stress
V
or
4200-901-01 Rev. S / May 2017
Invalid Test Result - Result = 1e21.
The following diagram from JESD35-A has been reproduced with permission from
JEDEC. This flowchart is JEDEC copyright protected material.
V-Ramp Flow Diagram
Force
V
use
I
Measure
use
Initial Failure
I
I
>
Yes
use
init
?
No
V
=
stress
start
Qbd = 0
V
Force
stress
I
Measure
I
>
meas
I
x 10
expect
I
or
at
meas
?
I
I
>10 *
meas
prev
No
Yes
I
>
No
I
crit
Calculate
No
Slope
V
V
=
crit
stress
I
t
+
*
bd
meas
interval
V
stress
V
V
=
+
stress
step
V
V
>
stress
max
> Compliance
stress
Q
Q
>
?
bd
max
Note: All values are absolute – no (+) or (-) signs have been incorporated.
Return to
V
Force
Measure
Stop Test
Type 1
I
>
meas
?
No
Non-Catastrophic Failure
Stop Test
Type 4
Optional Type 4
Classification
4.2 Reached Current
Compliance
V
Force
Yes
Yes
Measure
Yes
Fails slope
change
criteria?
I
>
meas
?
No
No
Other Failure
Yes
Stop Test
Type 5
Section Topics
Catastrophic
Failure
Stop Test
Type 2 (desired)
use
Yes
I
Optional Type 2
Classification
2.1 I
>
meas
I
2.2 I
at Compliance
meas
init
2.3 Failed Slope Criteria
Record
V
=
bd
q
Q
=
bd
Failure Type
Optionally Record:
I
bd
V
use
crit
I
use
Other Voltage/
Current Pairs
I
Optional Type 3
Classification
3.1 Q
Q
bd
3.3 Reached Voltage
Compliance/Maximum
I
init
Yes
Masked Catastrophic
Failure - Stop Test
Type 3
Optional Type 5
Classification
5.1 Q
Q
bd
5.3 Reached Voltage
Compliance/Maximum
Appendix M: WLR Testing
10 * I
prev
V
prev
/area
bd
max
max
M-13

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