Partial Reconfiguration - Altera cyclone V Technical Reference

A-34

Partial Reconfiguration

If the HPS resets in the middle of a normal configuration data transfer before entering user mode, software
can assume that the configuration is unsuccessful. After the HPS resets, software must repeat the steps for
full configuration.
1. Set the
match the characteristics of the configuration image. These settings are dependent on the
input.
2. Set the
3. Set the
signals.
4. Set the
portion of the device into the reset phase.
5. Poll the
6. Set the
7. Read the
8. Clear the interrupt bit of nSTATUS (ns) in the
regs.mon.gpio_porta_eoi
9. Set the
10.Write the configuration image to the configuration data register (
configuration data registers (
the configuration image from a peripheral device to the FPGA manager.
11.Use the
( ) bits.
ns
12.Set the
13.Clear any previous DONE status by writing a 1 to the
(
dclkstat
14.Send the
15.Poll the
all the
DCLKs
16.Write a 1 to the
17.Read the
18.Set the
Partial Reconfiguration
Partial reconfiguration allows you to reconfigure part of the device while other sections remain running.
The HPS performs partial reconfiguration while the FPGA portion of the device is in user mode. The
following sequence suggests one way for software to perform a partial configuration:
• If
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• If
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and bits of the
cdratio cfgwdth
bit of the register to 0 to enable HPS configuration.
nce ctrl
bit of the register to 1 to give the FPGA manager control of the configuration input
en ctrl
bit of the
nconfigpull ctrl
bit of the register and wait until the FPGA enters the reset phase.
mode stat
bit of the
nconfigpull ctrl
bit of the register and wait until the FPGA enters the configuration phase.
mode stat
).
bit of the
axicfgen ctrl
fpgamgrdata
fpgamgrregs.mon.gpio_ext_porta
bit of the
axicfgen ctrl
) to clear the completed status flag.
required by the FPGA to enter the initialization phase.
DCLKs
bit of the
dcntdone DCLK
have been sent.
bit of the
dcntdone
bit of the register to wait for the FPGA to enter user mode.
mode stat
bit of the register to 0 to allow the external pins to drive the configuration input signals.
en ctrl
=1, continue to step 7.
is 0, then go back and repeat step 5. Note that a minimum of 16
register in the FPGA manager registers (
ctrl
register to 1 to pull down the
register to 0 to release the FPGA from reset.
gpio interrupt
register to 1 to enable sending configuration data to the FPGA.
). You can also choose to use a DMA controller to transfer
registers to monitor the
register to 0 to disable configuration data on AXI slave.
dcntdone
status register (
dclkstat
status register to clear the completed status flag.
DCLK
pin and put the FPGA
nCONFIG
register (
fpgamgr-
) in the FPGA manager module
data
(
CONF_DONE cd
bit of the DCLK status register
) until it changes to 1, which indicates that
pulses are required.
DCLK
Booting and Configuration
cv_5v4
2016.10.28
) to
fpgamgrregs
pins
MSEL
) and
nSTATUS
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