L4 Watchdog 0 Timer - Altera cyclone V Technical Reference

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L4 Watchdog 0 Timer

for boot pins after a warm reset. This configuration on warm reset is enabled by programming the
register in the Boot ROM Code Register group of the System Manager.
L4 Watchdog 0 Timer
The boot ROM enables the L4 Watchdog 0 Timer early in the boot process.
This watchdog is reserved for the boot ROM until the preloader indicates that it has started correctly and
taken control of the exception vectors. The timeout is at least one second, depending on the clock select
setting. Because the watchdog is reset just before the control passes to preloader, the preloader must reset
the watchdog when it begins execution.
The L4 watchdog 0 timer is reserved for boot ROM use. While booting, if a watchdog reset happens before
software control passes to the preloader, the boot ROM code attempts to load the last valid preloader
image, identified by the
If the watchdog reset happens after the preloader has started executing but before it writes a valid value to
initswstate
watchdog reset happens after the preloader writes a valid value to
code attempts to load the image indicated by
Preloader
The function of the preloader is user-defined. However, typical functions include:
• Initializing the SDRAM interface
• Configuring the HPS I/O pins
• Initializing the interface that loads the next stage of software
Initializing the SDRAM allows the preloader to load the next stage of the boot software (that might not fit
in the 60 KB available in the on-chip RAM) into SDRAM. A typical next software stage is the open source
boot loader, U-boot. The preloader is allowed to load the next boot software stage from any device
available to the HPS. Typical sources include the same flash device that contains the preloader, a different
flash device, or a communication interface such as an EMAC.
U-Boot Loader
The optional U-boot loader loads the operating system and passes software control to the operating
system.
Boot ROM Flow
On a cold reset, the HPS boot process starts when CPU0 is released from reset (for example, on a power
up) and executes code in the internal boot ROM at the reset exception address. The boot ROM code brings
the SoC out of reset and into a known state. After boot ROM code is exited, control passes to the next
stage of the boot software, referred to as the preloader. The preloader can be customized and is typically
stored external to the HPS in a nonvolatile flash-based memory or in on-chip RAM within the FPGA.
Beyond that, another boot layer can be executed before loading the operating system software.
This section describes the software flow from reset until the boot ROM code passes software control to the
preloader.
The following figure illustrates that the boot ROM code can perform a warm boot from on-chip RAM, a
cold boot from the FPGA portion of the device, or a cold boot from flash memory.
Altera Corporation
initswlastld
register, the boot ROM increments
register in the System Manager.
initswlastld
register.
initswlastld
and attempts to load that image. If the
register, the boot ROM
initswstate
Booting and Configuration
cv_5v4
2016.10.28
ctrl
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